- Faculty of Engineering
- Department of Electronic & Telecommunication Engineering
- Senior Lecturer Grade I
Contact information
Department of Electronic & Telecommunication Engineering
Faculty of Engineering
University of Moratuwa
Moratuwa
10400
Teaching and Administrative Activities
Analog Circuit Design -Undergraduate -2015
Digital IC Design -Undergraduate -2015
Electronics III -Undergraduate -2015
Advance Digital System Laboratory -Undergraduate -2015
Circuits & System Design -Undergraduate -2016
Digital IC Design -Undergraduate -2016
Electronics III -Undergraduate -2016
Advance Digital System Laboratory -Undergraduate -2016
Digital IC Design -Undergraduate -2017
Circuit & System Design -Undergraduate -2017
Digital System Design -Postgraduate -2015
Digital System Design -Postgraduate -2017
member -Staff-Student Liaison Committee (2015 To 2016)
member -Staff-Student Liaison Committee (2016 To 2017)
member -Orientation Committee (2017 To date)
member -Quality Assurance Cell (2017 To date)
Research Activities
High Temperature Electronics
Digital IC Design
Analog IP Design
Noise Reduction Techniques
and HW/SW Partitioning
- High Temperature Electronics - Digital IC Design - Analog IP Design - Noise Reduction Techniques - HW/SW Partitioning
Education and Professional Affiliations
PhD, University of Hong Kong ,1999
Bachelors, University of Peradeniya ,1994
The Institute of Electrical and Electronics Engineers(2016 To date)
Career
R&D Consultant Swiss Ranks Singapore Sep 01 To Date (1Yr +)
Senior Lecturer - Gr 1 University of Moratuwa Sri Lanka Jan.2011 To Date (10 Yrs +)
Senior IC Design Engineer ST Microelectronics Singapore Jan. 2008 To July 2010 (2 Yrs 6M)
Senior IC Design Engineer Agilent Technologies Singapore Jan. 2000 To Jan. 2008 (8 Yrs)
Research Assistant University of Hong Kong Hong Kong Apr. 1996 To Dec. 1999 (3 Yrs 9M)
Engineer SriLanka Telecom Services Sri Lanka Jun. 1995 To Jan. 1996 (8 M)
Instructor University of Peradeniya Sri Lanka Jul. 1994 To Jun. 1995 (1Yr)
Honours and Awards
Publications*
Anuradha Nanayakkara,".Optimization of Receiver FIFO for IEEE 802.3ba 40GBASE PCS Sub Layer.",IEEE-ICOIN,Malaysia,2016,
MD Sudara, VS Wijesinghe, DM Serasinghe, JGDA Thilakaratne,".Implementation and analysis of fast locking 5GHz phase locked loop.",2016 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE),Malaysia,2016,16-20
Udara Piumal De Silva, Anusha Lokumarambage, Hasantha Malavipathirana, Chathuranga Mohottala,".IEEE 802.3 100Gbps Ethernet PCS IP design challenges and solutions.",2016 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE),Malaysia,2016,21-25
W.P. Ranjula, R.M.A.U. Senarath, D.P.D. Senaratna, G.D.S.P. Senaratne,".Implementation Techniques for IEEE 802.3ba 40Gbps Ethernet Physical Coding Sublayer (PCS).",ECTI-CON,Thailand,2015,
Other Details
